
CONTENTS
ii
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
5.5 Addressing Modes (without ext extension) ..................................................................... 22
5.5.1 Immediate Addressing ....................................................................................... 22
5.5.2 Register Direct Addressing ................................................................................
22
5.5.3 Register Indirect Addressing ..............................................................................
23
5.5.4 Register Indirect Addressing with Postincrement ..............................................
23
5.5.5 Register Indirect Addressing with Displacement ...............................................
24
5.5.6 Signed PC Relative Addressing ........................................................................
24
5.6 Addressing Modes with
ext ............................................................................................. 25
5.6.1 Extension of Immediate Addressing .................................................................. 25
5.6.2 Extension of Register Indirect Addressing .........................................................
26
5.6.3 Exception Handling for
ext
Instructions ............................................................
30
5.7 Data Transfer Instructions ................................................................................................
31
5.8 Logical Operation Instructions .......................................................................................... 32
5.9 Arithmetic Operation Instructions ..................................................................................... 33
5.10 Multiply Instructions ........................................................................................................ 34
5.11 Shift and Rotate Instructions .......................................................................................... 35
5.12 Bit Manipulation Instructions .......................................................................................... 36
5.13 Push and Pop Instructions ............................................................................................. 37
5.14 Branch and Delayed Branch Instructions ....................................................................... 39
5.14.1 Types of Branch Instructions ............................................................................ 39
5.14.2 Delayed Branch Instructions ............................................................................
42
5.15 System Control Instructions ...........................................................................................
44
5.16 Swap Instructions ........................................................................................................... 45
5.17 Other Instructions ........................................................................................................... 46
6 Functions ...................................................................................................................... 47
6.1 Transition of the Processor Status .................................................................................... 47
6.1.1 Reset State ........................................................................................................ 47
6.1.2 Program Execution State ...................................................................................
47
6.1.3 Exception Handling ............................................................................................
47
6.1.4 Debug Exception ................................................................................................
47
6.1.5 HALT and SLEEP Modes ...................................................................................
47
6.2 Program Execution ...........................................................................................................
48
6.2.1 Instruction Fetch and Execution ......................................................................... 48
6.2.2 Execution Cycles and Flags ...............................................................................
49
6.3 Interrupts and Exceptions ................................................................................................
52
6.3.1 Priority of Exceptions ......................................................................................... 52
6.3.2 Vector Table ........................................................................................................
53
6.3.3 Exception Handling ............................................................................................
54
6.3.4 Reset .................................................................................................................
54
6.3.5 Address Misaligned Exception ...........................................................................
54
6.3.6 NMI ....................................................................................................................
55
6.3.7 Software Exceptions ..........................................................................................
55
6.3.8 Maskable External Interrupts .............................................................................
55
6.3.9 Undefined Instruction Exception ........................................................................
56
6.3.10
ext
Exception .................................................................................................. 56
6.4 Power-Down Mode ...........................................................................................................
57
6.5 Debug Circuit ................................................................................................................... 58
6.6 Coprocessor Interface ...................................................................................................... 59
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