Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Pobierz pdf (Strona 135)

7 DETAILS OF INSTRUCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

127

ld.w [%sp + imm6], %rs

Function

Word data transfer

Standard) W[sp +

imm6 × 4] ← rs

Extension 1) W[sp +

imm19] ← rs

Extension 2) W[sp +

imm32] ← rs

Code

15 12 11 10 9 4 3 0

0 1 0 1 1 1

imm6 r s

0x5C__

Flag

IE C V Z N

– – – – –

Mode

Src: Register direct %rs = %r0 to %r15

Dst: Register indirect with displacement

CLK

Two cycle

Description

(1) Standard

ld.w [%sp +

imm6],%rs ; memory address = sp + imm6 × 4

The content of the rs register is transferred to the specified memory location. The content of

the current SP with four times the 6-bit immediate

imm6 added as displacement comprises the

memory address to be accessed. The two least significant bits of the displacement are always 0.

(2) Extension 1

ext

imm13 ; = imm19(18:6)

ld.w [%sp +

imm6],%rs ; memory address = sp + imm19,

;

imm6 = imm19(5:0)

The

ext instruction extends the displacement to a 19-bit quantity. As a result, the content of

the rs register is transferred to the address indicated by the content of the SP with the 19-bit

immediate imm19 added. Make sure the imm6 specified here resides on a word boundary (two

least significant bits = 0).

(3) Extension 2

ext

imm13 ; = imm32(31:19)

ext

imm13 ; = imm32(18:6)

ld.w [%sp +

imm6],%rs ; memory address = sp + imm32,

;

imm6 = imm32(5:0)

The two

ext instructions extend the displacement to a 32-bit quantity. As a result, the content

of the rs register is transferred to the address indicated by the content of the SP with the 32-bit

immediate imm32 added. Make sure the imm6 specified here resides on a word boundary (two

least significant bits = 0).

1 2 ... 130 131 132 133 134 135 136 137 138 139 140 ... 180 181

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