Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Strona 114

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7 DETAILS OF INSTRUCTIONS
106
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
ld.h %rd, [%sp + imm6]
Function
Signed halfword data transfer
Standard) rd(15:0)
H[sp + imm6 × 2], rd(31:16) H[sp + imm6 × 2](15)
Extension 1) rd(15:0)
H[sp + imm19], rd(31:16) H[sp + imm19](15)
Extension 2) rd(15:0)
H[sp + imm32], rd(31:16) H[sp + imm32](15)
Code
15 12 11 10 9 4 3 0
0 1 0 0 1 0
imm6 r d
0x48__
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Flag
IE C V Z N
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Mode
Src: Register indirect with displacement
Dst: Register direct
%rd = %r0 to %r15
CLK
Two cycles
Description
(1) Standard
ld.h
%rd,[%sp + imm6] ; memory address = sp + imm6 × 2
The halfword data in the specified memory location is transferred to the rd register after being
sign-extended to 32 bits. The content of the current SP with twice the 6-bit immediate
imm6
added as displacement comprises the memory address to be accessed. The least significant bit
of the displacement is always 0.
(2) Extension 1
ext imm13 ; = imm19(18:6)
ld.h
%rd,[%sp + imm6] ; memory address = sp + imm19,
;
imm6 = imm19(5:0)
The ext instruction extends the displacement to a 19-bit quantity. As a result, the content of the
SP with the 19-bit immediate imm19 added comprises the memory address, the halfword data in
which is transferred to the rd register. Make sure the
imm6 specified here resides on a halfword
boundary (least significant bit = 0).
(3) Extension 2
ext
imm13 ; = imm32(31:19)
ext
imm13 ; = imm32(18:6)
ld.h
%rd,[%sp + imm6] ; memory address = sp + imm32,
;
imm6 = imm32(5:0)
The two
ext instructions extend the displacement to a 32-bit quantity. As a result, the content
of the SP with the 32-bit immediate
imm32 added comprises the memory address, the halfword
data in which is transferred to the rd register. Make sure the
imm6 specified here resides on a
halfword boundary (least significant bit = 0).
Example
ext 0x1
ld.h %r0,[%sp + 0x2] ; r0
[sp + 0x42] sign-extended
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