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5 INSTRUCTION SET
18
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
5 Instruction Set
The C33 PE Core instruction set consists of the function-extended instruction set of the C33 STD Core CPU and
the new instructions, in addition to the conventional S1C33-series instructions. Some instructions of the C33 STD
Core CPU are deleted. As the C33 PE Core is object-code compatible with the C33 STD Core CPU, software assets
can be transported from the S1C33 series to the C33 PE model easily, with minimal modifications required.
All of the instruction codes are fixed to 16 bits in length which, combined with pipelined processing, allows most
important instructions to be executed in one cycle. For details, refer to the description of each instruction in the
latter sections of this manual.
5.1 S1C33-Series-Compatible Instructions
Table 5.1.1 S1C33-Series-Compatible Instructions
Classification
Arithmetic operation
Branch
Function
Addition between general-purpose registers
Addition of a general-purpose register and immediate
Addition of SP and immediate (with immediate zero-extended)
Addition with carry between general-purpose registers
Subtraction between general-purpose registers
Subtraction of general-purpose register and immediate
Subtraction of SP and immediate (with immediate zero-extended)
Subtraction with carry between general-purpose registers
Arithmetic comparison between general-purpose registers
Arithmetic comparison of general-purpose register and immediate
(with immediate zero-extended)
Signed integer multiplication (16 bits
× 16 bits → 32 bits)
Unsigned integer multiplication (16 bits × 16 bits → 32 bits)
Signed integer multiplication (32 bits
× 32 bits → 64 bits)
Unsigned integer multiplication (32 bits
× 32 bits → 64 bits)
PC relative conditional jump Branch condition: !Z & !(N ^
V)
Delayed branching possible
PC relative conditional jump Branch condition: !(N ^
V)
Delayed branching possible
PC relative conditional jump Branch condition: N ^
V
Delayed branching possible
PC relative conditional jump Branch condition: Z | N ^ V
Delayed branching possible
PC relative conditional jump Branch condition: !Z & !C
Delayed branching possible
PC relative conditional jump Branch condition: !C
Delayed branching possible
PC relative conditional jump Branch condition:
C
Delayed branching possible
PC relative conditional jump Branch condition: Z | C
Delayed branching possible
PC relative conditional jump Branch condition: Z
Delayed branching possible
PC relative conditional jump Branch condition: !Z
Delayed branching possible
PC relative jump
Delayed branching possible
Absolute jump Delayed branching possible
PC relative subroutine call
Delayed call possible
Absolute subroutine call Delayed call possible
Subroutine return
Delayed return possible
Return from interrupt or exception handling
Return from the debug processing routine
Software exception
Debug exception
add
adc
sub
sbc
cmp
mlt.h
mltu.h
mlt.w
mltu.w
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
jp
jp.d
call
call.d
ret
ret.d
reti
retd
int
brk
%rd,%rs
%rd,imm6
%sp,imm10
%rd,%rs
%rd,%rs
%rd,imm6
%sp,imm10
%rd,%rs
%rd,%rs
%rd,sign6
%rd,%rs
%rd,%rs
%rd,%rs
%rd,%rs
sign8
sign8
sign8
sign8
sign8
sign8
sign8
sign8
sign8
sign8
sign8
%rb
sign8
%rb
imm2
Mnemonic
- S1C33 Family C33 PE 1
- CONTENTS 5
- 1 Summary 9
- 1.2.1 Instructions 10
- 1.2.2 Registers 11
- 2 Registers 12
- Processor Status Register 13
- 2 REGISTERS 14
- EPSON 14
- 2.4 Stack Pointer (SP) 15
- 0xFFFFFFFF 16
- 0x00000000 16
- 0x00060000 18
- 2.9.2 Special Registers 20
- Byte 38-bit data 21
- SSSSSSSS 22
- Example: ld.w %rd,%rs 24
- Example: ld.w %rd,[%rb] 24
- Example: ld.w [%rb],%rs 24
- 4 Address Map 25
- 5 Instruction Set 26
- 5 INSTRUCTION SET 27
- Table 5.1.2 Symbol Meanings 27
- 5.4 Instructions Removed 29
- 5.5.1 Immediate Addressing 30
- Extension of imm6 33
- Extension of sign6 33
- Adding displacement to [%rb] 34
- 00000000 35
- Data + imm26 36
- New address 37
- 5.10 Multiply Instructions 42
- Before execution of pushn 45
- Before execution of push 46
- Before execution of pop 46
- Branch destination address 47
- 5.16 Swap Instructions 53
- 5.17 Other Instructions 54
- 6 Functions 55
- 6.2 Program Execution 56
- 6 FUNCTIONS 57
- Added instructions 59
- 6.3.1 Priority of Exceptions 60
- TTBR[31:10] 61
- Vector code (10 bits) 61
- 6.3.3 Exception Handling 62
- 6.3.4 Reset 62
- 6.3.6 NMI 63
- 6.3.7 Software Exceptions 63
- 6.3.10 ext Exception 64
- 6.4 Power-Down Mode 65
- 6.5 Debug Circuit 66
- 6.6 Coprocessor Interface 67
- 7 Details of Instructions 68
- IE C V Z N 100
- (after execution) 156
- Sign bit 166
- 8 716 1524 23 173
- (in Order of Codes) 177
- Class 4 (1) 179
- Class 4 (2) 179
- Class 5 (1) 179
- Class 5 (2) 179
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