Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Pobierz pdf (Strona 55)

6 FUNCTIONS

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

6 Functions

This chapter describes the processing status of the C33 PE Core and outlines the operation.

6.1 Transition of the Processor Status

The diagram below shows the transition of the operating status in the C33 PE Core.

Program execution state

Exception

handling

Debug

exception

handling

Sleep mode

Reset state

Halt mode

slp

instruction

trap

Debug

exception

retd

instruction

Exception

reti

instruction

halt

instruction

trap

Figure 6.1.1 Processor Status Transition Diagram

6.1.1 Reset State

The processor is initialized when the reset signal is asserted, and then starts processing from the reset vector when

the reset signal is deasserted.

6.1.2 Program Execution State

This is a state in which the processor executes the user program sequentially. The processor state transits to another

when an exception occurs or the

slp or halt instruction is executed.

6.1.3 Exception Handling

When a software or other exception occurs, the processor enters an exception handling state. The following are the

possible causes of the need for exception handling:

(1) External interrupt

(2) Software exception

(3) Address misaligned exception

(4) Zero division

(5) NMI

(6) Undefined instruction exception/

ext exception

6.1.4 Debug Exception

The C33 PE Core incorporates a debugging assistance facility to increase the efficiency of software development.

To use this facility, a dedicated mode known as “debug mode” is provided. The processor can be switched from user

mode to this mode by the brk instruction or a debug exception. The processor does not normally enter this mode.

6.1.5 HALT and SLEEP Modes

The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp

instruction in the software (see Section 6.4). Normally the processor can be taken out of HALT or SLEEP mode by

NMI or an external interrupt as well as initial reset.

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