Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Strona 40

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5 INSTRUCTION SET
32
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
5.8 Logical Operation Instructions
Four discrete logical operation instructions are available for use with the C33 PE Core.
and Logical AND
or Logical OR
xor Exclusive-OR
not Logical NOT
All logical operations are performed in a specified general-purpose register (R0–R15). The source is one of two,
either 32-bit data in a specified general-purpose register or signed immediate data (6, 19, or 32 bits).
Differences from the C33 STD Core CPU
When a logical operation is performed, the V flag (bit 2) in the PSR is cleared.
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