Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Pobierz pdf (Strona 50)

5 INSTRUCTION SET

EPSON

S1C33 FAMILY C33 PE CORE MANUAL

5.14.2 Delayed Branch Instructions

The C33 PE Core uses pipelined instruction processing, in which instructions are executed while other instructions

are being fetched. In a branch instruction, because the instruction that follows it has already been fetched when it

is executed, the execution cycles of the branch instruction can be reduced by one cycle by executing the prefetched

instruction before the program branches. This is referred to as a delayed branch function, and the instruction

executed before branching (i.e., the instruction at the address next to the branch instruction) is referred to as a

delayed slot instruction.

The delayed branch function can be used in the instructions listed below, which in mnemonics is identified by the

extension “

.d” added to the branch instruction name.

Delayed branch instructions

jrgt.d jrge.d jrlt.d jrle.d jrugt.d jruge.d jrult.d

jrule.d jreq.d jrne.d call.d jp.d ret.d jpr.d

Delayed slot instructions

It is necessary that the delayed slot instructions satisfy all of the following conditions:

• 1-cycle instruction

• Do not access memory

• Not extended by an

ext instruction

The instructions listed below can be used as delayed slot instructions:

ld.b %rd,%rs

ld.ub %rd,%rs

ld.h %rd,%rs

ld.uh %rd,%rs

ld.w %rd,%rs ld.w %rd,sign6

add %rd,%rs add %rd,imm6 add %sp,imm10

adc %rd,%rs

sub %rd,%rs sub %rd,imm6 sub %sp,imm10

sbc %rd,%rs

cmp %rd,%rs cmp %rd,sign6

and %rd,%rs and %rd,sign6

or %rd,%rs or %rd,sign6

xor %rd,%rs xor %rd,sign6

not %rd,%rs not %rd,sign6

srl %rd,%rs srl %rd,imm5

sll %rd,%rs sll %rd,imm5

sra %rd,%rs sra %rd,imm5

sla %rd,%rs sla %rd,imm5

rr %rd,%rs rr %rd,imm5

rl %rd,%rs rl %rd,imm5

swap %rd,%rs swaph %rd,%rs

ld.c %rd,imm4

ld.c imm4,%rs

Note: Unless the above conditions are satisfied, the instruction may operate unstably. Therefore, it is

prohibited to use such instructions as delayed slot instructions.

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 180 181

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