Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Pobierz pdf (Strona 179)

APPENDIX INSTRUCTION CODE LIST (IN ORDER OF CODES)

S1C33 FAMILY C33 PE CORE MANUAL

EPSON

171

Class 4 (1)

add %sp,imm10

sub %sp,imm10

Class

op1

imm10

Mnemonic

Extension

Delayed S

imm10

Cycle

Class 4 (2)

srl %rd,imm5

srl %rd,%rs

sll %rd,imm5

sll %rd,%rs

sra %rd,imm5

sra %rd,%rs

swap %rd,%rs

sla %rd,imm5

sla %rd,%rs

rr %rd,imm5

rr %rd,%rs

swaph %rd,%rs

rl %rd,imm5

rl %rd,%rs

Class

op1

imm5,rs

op2

Mnemonic

Extension

Delayed S

imm5(3:0)

Cycle

Class 5 (1)

imm3

ld.w %sd,%rs

ld.b %rd,%rs

mlt.h %rd,%rs

ld.w %rd,%ss ∗1

ld.ub %rd,%rs

mltu.h %rd,%rs

btst [%rb],imm3

ld.h %rd,%rs

mlt.w %rd,%rs

bclr [%rb],imm3

ld.uh %rd,%rs

mltu.w %rd,%rs

bset [%rb],imm3

ld.c %rd,imm4

bnot [%rb],imm3

ld.c imm4,%rs

adc %rd,%rs

sbc %rd,%rs

Class

op1

imm4,r,s

imm3,r,s

op2

Mnemonic

Extension

Delayed S

imm4

1,3(psr)

2,3(ext

)

3,4(ext

)

3,4(ext

)

3,4(ext

)

Cycle

Class 5 (2)

imm5

do.c imm6

psrset imm5

psrclr imm5

Class

op1

imm5,imm6

op2

Mnemonic

Extension

Delayed S

imm6

op3

Cycle

Class 6

ext imm13

Class

imm13

Mnemonic

Extension

Delayed S

imm13

0,1

Cycle

Inst Function-Extended Instructions

Inst Added Instructions

∗1 The ld.w %rd,%pc instruction must be executed as a delayed slot instruction. If it does not follow a delayed

branch instruction, the PC value that is loaded into the rd register may not be the next instruction address to the

ld.w instruction.

1 2 ... 174 175 176 177 178 179 180 181

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