Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Instrukcja Użytkownika Pobierz pdf (Strona 142)

7 DETAILS OF INSTRUCTIONS

134

EPSON

S1C33 FAMILY C33 PE CORE MANUAL

not %rd, sign6

Function

Logical negation

Standard) rd

← !sign6

Extension 1) rd

← !sign19

Extension 2) rd

← !sign32

Code

15 12 11 10 9 4 3 0

0 1 1 1 1 1

sign6 r d

0x7C__

Flag

IE C V Z N

– – 0

↔ ↔

Mode

Src: Immediate data (signed)

Dst: Register direct

%rd = %r0 to %r15

CLK

One cycle

Description

(1) Standard

not

%rd,sign6 ; rd ← !sign6

All the bits of the sign-extended 6-bit immediate sign6 are reversed, and the result is loaded into

the rd register.

(2) Extension 1

ext imm13 ; = sign19(18:6)

not

%rd,sign6 ; rd ← !sign19, sign6 = sign19(5:0)

All the bits of the sign-extended 19-bit immediate

sign19 are reversed, and the result is loaded

into the rd register.

(3) Extension 2

ext

imm13 ; = sign32(31:19)

ext

imm13 ; = sign32(18:6)

not

%rd,sign6 ; rd ← !sign32, sign6 = sign32(5:0)

All the bits of the sign-extended 32-bit immediate

sign32 are reversed, and the result is loaded

into the rd register.

(4) Delayed instruction

This instruction may be executed as a delayed instruction by writing it directly after a branch

instruction with the “d” bit. In this case, extension of the immediate by the ext instruction

cannot be performed.

Example

(1) not %r0,0x1f ; r0 = 0xffffffe0

(2)

ext 0x7ff

not %r1,0x3f ; r1 = 0xfffe0000

1 2 ... 137 138 139 140 141 142 143 144 145 146 147 ... 180 181

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