Epson S1C6200A Dokumentacja Pobierz pdf (Strona 197)

S1C62740 TECHNICAL SOFTWARE EPSON II-45

CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer)

Programmable timer control

The PTRST bit resets the programmable timer.

By writing "1" on PTRST, the programmable timer is reset. The

contents set in reload registers RD0–RD7 are loaded into the down-

counter.

The PTRUN bit controls RUN/STOP of the programmable timer.

By writing "1" on PTRUN, the programmable timer performs count-

ing operation. Writing "0" will make the programmable timer stop

counting.

When the programmable timer is reset in the RUN status, it will re-

start counting immediately after loading and at STOP status, the

load data is maintained.

Programmable timer data

The data from the down-counter of the programmable timer can be

read out with PT0–PT3 (low-order 4 bits) and PT4–PT7 (high-order

4 bits).

Programmable timer interrupt

When the down-counter values PT0–PT7 have become 00H the

interrupt factor flag IPT is set to "1" and an interrupt is generated.

The interrupt can be masked through the interrupt mask register

EIPT. However, regardless of the setting of the interrupt mask

counter equals 00H.

Note:

PTRST

PTRUN

Count clock

Timer data

high-order

address

(ECH)

Timer data

low-order

address

(EBH)

PTOVF

Interrupt request Interrupt request Interrupt request

• When "A6H" is set into the reload register.

• The count clock is output from the predivider.

Fig. 6.9.2

Timing chart for

programmable timer

1 2 ... 192 193 194 195 196 197 198 199 200 201 202 ... 248 249

Komentarze do niniejszej Instrukcji

Brak uwag

Epson S1C6200A Dokumentacja Strona 197

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Nie Epson S1C6200A