Epson S1C6200A Dokumentacja Strona 15
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S1C62740 TECHNICAL HARDWARE EPSON I-3
CHAPTER 1: OVERVIEW
Block Diagram1.2
Fig. 1.2.1
Block diagram
LOGIC
POWER
CONTROL
and SVD
INTERRUPT
CONTROL
PROG.
TIMER or
EVENT
COUNTER
K00–K03
K10
RAM
512 x 4
COM0–
COM3
SEG0–
SEG31
DD
CA
C1
C2
C3
D1
SS
P00–P03
P10–P13
P20–P23
SYSTEM
RESET
CONTROL
ROM
4,096 x 12
CORE CPU S1C6200A
OSC
and
SLEEP
LCD
DRIVER
32 x 4
OSC1
OSC2
OSC3
OSC4
ANALOG
POWER
CONTROL
DDA
RA
R1
R2
SSA
A/D
CONVERTER
AI0
AI1
AI2
AI3
AI4
AIF
BF
RI
CI
CAZ
CO
OP-AMP
AIP0, 1
AIM0, 1
AOUT0, 1
TIMER
STOP
WATCH
OUTPUT
PORT
INPUT
PORT
I/O
PORT
FOUT &
BUZZER
SERIAL
I/O PORT
RESET
TEST
R00–R03
S1C62740 BLOCK DIAGRAM
V
V
V
V
V
CA
CB
CC
V
V
V
V
V
V
CH
CL
GND
V
- S1C62740 1
- Technical Hardware 7
- CONTENTS 10
- Hardware 11
- OVERVIEW 13
- CHAPTER 1 13
- Features1.1 14
- S1C62740 BLOCK DIAGRAM 15
- 1.3 Pin Layout Diagram 16
- 1.4 Pin Description 18
- 2.1 Power Supply 19
- C RA1 RA2 20
- Initial Reset 21
- Reset terminal 22
- Simultaneous low 22
- Watchdog timer 23
- Internal register at 23
- (TEST and CO) 23
- CPU, ROM, RAMCHAPTER 3 24
- EPSON I-13 25
- CHAPTER 3: CPU, ROM, RAM 25
- PERIPHERAL CIRCUITS AND 26
- OPERATION 26
- CHAPTER 4 26
- EPSON I-15 27
- Memory map 27
- EPSON I-17 29
- EPSON I-19 31
- Resetting Watchdog Timer4.2 32
- Control of watchdog 33
- Programming note 33
- Oscillation Circuit4.3 34
- OSC3 oscillation 35
- Control of oscillation 36
- Clock frequency 37
- Input Ports (K00–K03, K10)4.4 38
- Interrupt function 39
- Mask option 41
- Control of input ports 42
- EPSON I-31 43
- Output Ports (R00–R03)4.5 45
- • BZ and BZ 46
- (R02 and R03) 46
- R00 register 47
- FOUT output 47
- Control of output 48
- EPSON I-37 49
- Configuration of I/O 51
- Control of I/O ports 53
- Configuration of LCD 56
- EPSON I-45 57
- Fig. 4.7.1 57
- Drive waveform 57
- LCD display ON/OFF 59
- (segment allocation) 60
- n and SEG2 61
- Clock Timer4.8 63
- Control of clock 65
- Stopwatch Timer4.9 68
- Count-up pattern 69
- Control of stopwatch 71
- Programmable Timer4.10 74
- K10 input 75
- Down count 75
- Down counter = 00H 76
- Control of 78
- EPSON I-67 79
- PTD1 PTD0 Dividing ratio 79
- Table 4.10.5 79
- (SIN, SOUT, SCLK, SRDY)4.11 82
- Master mode and 83
- Data input/output 84
- (4) SRDY signal 85
- EPSON I-75 87
- Table 4.11.3 88
- Synchronous clock selection 88
- • During writing operation 89
- • During reading operation 89
- A/D Converter4.12 92
- • Voltage measurement 93
- • Resistance measurement 93
- (1) Voltage measurement 93
- (3) Resistance measurement 94
- DD side using a GND 95
- Reference voltage 96
- R1 andVR2 97
- Middle electric 98
- Operation of the 99
- Input integration period 100
- Auto zero adjustment period 100
- • When the input voltage V 101
- • Voltage measurement mode 102
- • Resistance measurement mode 103
- A/D conversion and 104
- Control of the A/D 108
- EPSON I-99 111
- Programming notes 112
- Configuration of 113
- AMP circuit 113
- Operation of AMP 113
- Control of AMP 114
- Configuration of SVD 115
- SVD operation 115
- Control of SVD 116
- Interrupt and HALT/SLEEP 118
- EPSON I-107 119
- Fig. 4.15.1 119
- Interrupt factor 120
- Interrupt mask 121
- Note: The processing in 122
- Control of interrupt 123
- SUMMARY OF NOTESCHAPTER 5 126
- EPSON I-115 127
- CHAPTER 5: SUMMARY OF NOTES 127
- EPSON I-117 129
- Interrupt and HALT/ 130
- DIAGRAM OF BASIC EXTERNAL 131
- CONNECTIONS 131
- CHAPTER 6 131
- 7.1 Absolute Maximum Rating 133
- DC Characteristics 134
- R2 are not included 136
- Zero point error E 137
- Porality error E 137
- Linearity error EL 137
- Input voltage range 140
- OSC3 CR oscillation circuit 141
- PACKAGECHAPTER 8 142
- QFP15-100pin 143
- (Unit: mm) 144
- PAD LAYOUTCHAPTER 9 145
- 9.2 Pad Coordinates 146
- Software 147
- INTRODUCTION 153
- BLOCK DIAGRAM 154
- CHAPTER 2 154
- PROGRAM MEMORY (ROM)CHAPTER 3 155
- DATA MEMORYCHAPTER 4 156
- EPSON II-5 157
- CHAPTER 4: DATA MEMORY 157
- Fig. 4.1.1 157
- Data memory map 157
- Detail Map of the I/O Memory 158
- EPSON II-7 159
- EPSON II-9 161
- INITIAL RESETCHAPTER 5 162
- Initialization 163
- CHAPTER 5: INITIAL RESET 164
- CHAPTER 6 PERIPHERAL CIRCUITS 165
- Example program 166
- Programing notes 166
- I/O data memory of 167
- Control of the OSC3 167
- Control of the input 170
- Output Ports (R00–R03)6.4 174
- Control of the 176
- Control of the I/O 179
- EPSON II-29 181
- Fig. 6.5.2 181
- Control of I/O port (Input) 181
- Fig. 6.5.3 182
- Control of I/O port (Output) 182
- Serial I/O port 183
- LCD Driver6.6 184
- Register 185
- DisplayA resister 186
- Clock Timer6.7 188
- Stopwatch Timer6.8 191
- EPSON II-41 193
- Programmable Timer6.9 195
- Programmable timer control 197
- Programmable timer data 197
- Programmable timer interrupt 197
- Timer data 198
- Timer overflow (reload) 198
- EPSON II-47 199
- Serial Interface Circuit6.10 201
- Serial data output 202
- Serial data input 202
- EPSON II-53 205
- Amplifier6.11 207
- Control of the SVD 209
- A/D Converter6.13 211
- Feature of the A/D 212
- (even though ADON 213
- EPSON II-63 215
- Sleep6.14 217
- EPSON II-67 219
- Interrupt6.15 221
- Fig. 6.15.1 222
- EPSON II-73 225
- SUMMARY OF NOTESCHAPTER 7 228
- EPSON II-77 229
- CHAPTER 7: SUMMARY OF NOTES 229
- EPSON II-79 231
- Serial interface 232
- EPSON II-81 233
- APPENDIX A 234
- EPSON II-83 235
- RAM map - 2 (100H–17FH) 235
- RAM map - 3 (200H–27FH) 236
- EPSON II-85 237
- RAM map - 4 (300H–37FH) 237
- B S1C62740 INSTRUCTION SET 239
- Instruction set - 2 240
- EPSON II-89 241
- Instruction set - 3 241
- Symbols associated with 242
- EPSON II-91 243
- ASSEMBLER 244
- D COMMAND TABLE OF ICE 245
- ICE command table - 2 246
- Epson IS energy savings 248
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