Epson Powerspan Instrukcja Użytkownika Pobierz pdf (Strona 8)

DIMM.AM335x (Rev3) 8/24

Hardware write protection of the NOR flash is realized by the port pin GPIO3_4 of the processor. A

low level protects the flash device. During and after Reset the pin is driven low by the processor.

Besides the hardware protection the chip also supports a software protection.

Watch:

The processor operates in little-endian mode while the serial NOR flash operates in big-endian

mode (MSB first). The image data must be stored in the flash in big-endian format because the

processor does not convert the endianess of the data.

3.3 NAND Flash

The NAND Flash interface of the board is built from a flash controller S6 from Hyperstone and an

SLC NAND flash chip.

The S6 is connected to the MMC1 interface of the processor. It behaves as an SD Card that

conforms to SD Physical Layer specification 3.0. NAND Flash chips from various manufacturers with

up to 8 GByte capacity can be connected.

The standard flash capacity is 256 MByte.

3.4 DDR SDRAM

256 MByte or 512 MByte DDR3 SDRAM are soldered.

The RAM is clocked with 303 MHz and accessed with CAS latency 5. The data bus is 16 bit wide.

The RAM is located in the address range 0x8000_0000 … 0xBFFF_FFFF. The address range spans 1

GB. Smaller memories are mirrored within that range.

3.5 Processor Bus Interface

The processor bus interface is not available at the SODIMM connector since most of the pins are

multiplexed with pins of peripheral functions.

3.6 Ethernet

Two 100Base-TX Ethernet interfaces are incorporated in the CPU AM335x. Because of the pin

multiplexing only RMII1 interface is available.

An Ethernet PHY DP83848K from Texas Instruments is used. The PHY address is 1. A 50 MHz

oscillator is used as reference clock of the RMII interface.

The Ethernet signal line pairs ETH_TDP/ETH_TDM and ETH_RDP/ETH_RDM as well as two status

signals SPEED_LED# and LINK_LED# are connected to the SODIMM connector.

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Epson Powerspan Instrukcja Użytkownika Strona 8