Epson Powerspan Instrukcja Użytkownika Pobierz pdf (Strona 7)

DIMM.AM335x (Rev3) 7/24

3.1.2 Boot Mode

The processor AM335x has an integrated Boot ROM which supports 31 different boot

configurations. Each configuration consists of a sequence of 4 different boot devices that are

checked in series for valid boot data. The configuration is selected by the five configuration pins

SYSBOOT[4:0].

The following sequences are preferred:

 SPI0 – MMC0 – UART0 – EMAC1 0x16

 EMAC1 –SPI0 – NAND – NANDI2C 0x06

In normal operation a serial NOR flash which is connected to SPI0 is used as primary boot device.

For development and production purposes EMAC1 can be selected as primary boot medium

The boot sequence is selected via the two DIP Switches SW1-2 and SW1-1:

SW1-2

SW1-1

Boot device

off

SPI0

off

EMAC1

off

USB0

UART0

Watch: Booting from the eMMC/NAND connected to the MMC1 interface is not possible!

3.1.3 Interrupts

The processor AM335x incorporates an integrated interrupt controller. It processes incoming

interrupts by masking and priority sorting to produce the interrupt signals for the CPU.

4 GPIO pins are used to cause unique interrupt requests for the PMIC and 3 external devices

connected at the SODIMM connector.

AM335x GPIO

Source

GPIO1_16

PMIC

GPIO0_6

SODIMM NMI

GPIO2_26

SODIMM IRQ-A

GPIO3_0

SODIMM IRQ-B

The signalling level of all interrupts is 3.3V. The interrupts can be programmed to be edge or level

sensitive.

3.2 NOR-Flash

An 8 MByte serial NOR flash of type MX25L6445M2I-10G von Macronix is used as primary boot

device. It is connected to the interface SPI0.

The integrated bootloader of the processor supports booting from the NOR flash. Booting from

NOR Flash is enabled if DIP switch SW1-1 is off.

1 2 3 4 5 6 7 8 9 10 11 12 ... 23 24

Komentarze do niniejszej Instrukcji

Brak uwag

Epson Powerspan Instrukcja Użytkownika Strona 7

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Części komputerowe Epson Powerspan