Epson 6200A Instrukcja Użytkownika Strona 1
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- Spis treści
- BOOKMARKI
- S1C6200/6200A 1
- S1C6200/6200A Core CPU Manual 5
- 1DESCRIPTION 7
- 4-bit data bus 8
- 2MEMORY AND OPERATIONS 9
- 2.1.1 Program counter block 10
- 2.1.2 Flags 10
- 2.1.3 Jump instructions 11
- 2.1.5 Call instructions 11
- 2.1.6 PSET instruction 12
- 2.1.7 CALZ instruction 12
- Bank 0 Page 10 13
- Bank 0 Page 0 13
- Program memory 13
- 2.2 Data Memory 14
- • Index register IY 15
- • Stack pointer SP 15
- • Register pointer RP 15
- 2 MEMORY AND OPERATIONS 16
- 2.4 Timing Generator 17
- 2.5 Interrupts 18
- S1C6200A 19
- 2.5.4 Initial reset 21
- 3INSTRUCTION SET 22
- 3.1.1 By function 23
- 3 INSTRUCTION SET 24
- EPSON 19 25
- 3.1.2 In alphabetical order 26
- EPSON 21 27
- 3.1.3 By operation code 29
- EPSON 25 31
- 3.2 Operands 32
- 3.3 Flags 32
- 3.4 Instruction Types 33
- 3.5 Instruction Descriptions 33
- 1 r0 F28H to F2BH 34
- 1 r0 F2CH to F2FH 34
- 3 to i0 + C 35
- 1 r0 i3 i2 i1 i0 C40H to C7FH 35
- 1 r0 q1 q0 A90H to A9FH 35
- 3 i2 i1 i0 A00H to A0FH 36
- 3 i2 i1 i0 A10H to A1FH 36
- 3 i2 i1 i0 A20H to A2FH 37
- 3 i2 i1 i0 A30H to A3FH 37
- Add q-register to r-register 38
- 1 r0 i3 i2 i1 i0 C80H to CBFH 39
- 1 r0 q1 q0 AC0H to ACFH 39
- CALL s Call subroutine 40
- 1 r0 i3 i2 i1 i0 DC0H to DFFH 41
- 3 to i0; otherwise, reset 41
- 1 r0 q1 q0 F00H to F0FH 41
- Decrement stack pointer 44
- Decrement memory 44
- DI Disable interrupts 45
- EI Enable interrupts 45
- 1 r0 i3 i2 i1 i0 D80H to DBFH 46
- 1 r0 q1 q0 F10H to F1FH 46
- INC Mn Increment memory by 1 47
- HALT Halt 47
- Increment X-register by 1 48
- Increment Y-register by 1 49
- JP NC,s Jump if not carry 50
- JP NZ,s Jump if not zero 51
- JP s Jump 51
- JP Z,s Jump if zero 52
- Load memory into A-register 53
- Load memory into B-register 53
- Load A-register into memory 54
- Load B-register into memory 54
- 3 to i0, X ← X + 1 55
- 3 i2 i1 i0 E60H to E6FH 55
- 1 r0 q1 q0 EE0H to EEFH 55
- 3 to i0, Y ← Y + 1 56
- 3 i2 i1 i0 E70H to E7FH 56
- 1 r0 q1 q0 EF0H to EFFH 56
- 1 r0 i3 i2 i1 i0 E00H to E3FH 57
- 1 r0 q1 q0 EC0H to ECFH 57
- Load SPH into r-register 58
- Load SPL into r-register 58
- Load XH into r-register 59
- Load XL into r-register 59
- Load XP into r-register 60
- Load YH into r-register 60
- Load YL into r-register 61
- Load YP into r-register 61
- Load r-register into SPH 62
- Load r-register into SPL 62
- Load r-register into XH 63
- Load r-register into XL 64
- Load r-register into XP 64
- Load r-register into YH 65
- Load r-register into YL 66
- Load r-register into YP 66
- 1 r0 1 1 1 1 D0FH to D3FH 68
- Pop stack data into flags 69
- Pop stack data into XH 70
- Pop stack data into XL 71
- Pop stack data into XP 71
- Pop stack data into YH 72
- Pop stack data into YL 72
- PSET p Page set 73
- PUSH F Push flag onto stack 74
- PUSH XH Push XH onto stack 75
- PUSH XL Push XL onto stack 75
- PUSH XP Push XP onto stack 76
- PUSH YH Push YH onto stack 76
- PUSH YL Push YL onto stack 77
- PUSH YP Push YP onto stack 77
- RCF Reset carry flag 78
- RDF Reset decimal flag 78
- RET Return from subroutine 79
- 1 r0 r1 r0 AF0H to AFFH 80
- EPSON 75 81
- Memory (MY) 1010 1101 81
- C flag 1 0 81
- Flags (I,D,Z,C) 1010 0010 81
- RZF Reset zero flag 82
- SCF Set carry flag 83
- 1 r0 F38H to F3BH 84
- 1 r0 F3CH to F3FH 84
- SDF Set decimal flag 85
- SLP Sleep 86
- SZF Set zero flag 87
- 1 r0 q1 q0 AE0H to AEFH 88
- ABBREVIATIONS 89
- A1 Outline of Differences 90
- System clock 91
- CPU clock 91
- Instruction 91
- APPENDIX B. INSTRUCTION INDEX 93
- EPSON 89 95
Podsumowanie treści
MF297-07aCore CPU ManualCMOS 4-BIT SINGLE CHIP MICROCOMPUTERS1C6200/6200A
4 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONS2.1.1 Program counter blockThe program counter is used to point to the next instruction s
S1C6200/6200A CORE CPU MANUAL EPSON 52 MEMORY AND OPERATIONS2.1.3 Jump instructionsA jump can be made using the instructions in Table 2.1.3.1.Table 2
6 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONS2.1.6 PSET instructionJump or call instructions must follow PSET immediately in order for
S1C6200/6200A CORE CPU MANUAL EPSON 72 MEMORY AND OPERATIONSThe difference between CALL and CALZ is shown in Figure 2.1.7.2.Page 15Bank 0Page 14PSETC
8 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONS2.2 Data MemoryThe data memory area comprises 4,096 4-bit words. The RAM, timer, I/O and
S1C6200/6200A CORE CPU MANUAL EPSON 92 MEMORY AND OPERATIONS • Index register IYIndex register IY is like the index register IX: it has a4-bit page
10 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONS2.3 ALU (Arithmetic Logic Unit) and RegistersTable 2.3.1 shows ALU operations between th
S1C6200/6200A CORE CPU MANUAL EPSON 112 MEMORY AND OPERATIONSHexadecimal operations will not always produce the correct result if performed in decima
12 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONS2.5 InterruptsThe S1C6200/6200A can have up to 15 interrupt vectors. When used with peri
S1C6200/6200A CORE CPU MANUAL EPSON 132 MEMORY AND OPERATIONSFig. 2.5.3.1 Interrupt timing during executionClockStatusInstructionFetch5-clock Instrr
NOTICENo part of this material may be reproduced or duplicated in any form or by any means without the written permission of SeikoEpson. Seiko Epson r
14 EPSON S1C6200/6200A CORE CPU MANUAL2 MEMORY AND OPERATIONSFig. 2.5.3.3 Interrupt timing in SLEEP modeFig. 2.5.3.4 Interrupt timing with PSETFetc
S1C6200/6200A CORE CPU MANUAL EPSON 152 MEMORY AND OPERATIONSProgram Counter StepProgram Counter PageProgram Counter BankNew Page PointerNew Bank Poi
16 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SET3INSTRUCTION SETThis chapter describes the entire instruction set of the S1C6200/6200A Core CP
S1C6200/6200A CORE CPU MANUAL EPSON 173 INSTRUCTION SET3.1.1 By functionB100000100110111111111111111111111111A100011111110111111001111111111110000910
18 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SETB1111111111111111111111111111111111111111A0000111111111101111111111111111111111111911111111111
S1C6200/6200A CORE CPU MANUAL EPSON 193 INSTRUCTION SET↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓B111111111111111111111111111111111A11111111010010101010111101111111
20 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SET3.1.2 In alphabetical orderB11111111111100111111111111111111000001A111000001010111100001111111
S1C6200/6200A CORE CPU MANUAL EPSON 213 INSTRUCTION SETB11111111111111111111111111111111111111111A111111111111111111101110111111110111111119111111111
22 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SETB111111111111011111111111111111A11111111111101011110111111011091111111111110111110111111111018
S1C6200/6200A CORE CPU MANUAL EPSON 233 INSTRUCTION SET3.1.3 By operation codeB0000000011111111111111111111111111111A00001111000000000000000000011111
S1C60/62 FamilyDevicesS1 C 60N01 F 0A01Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : T
24 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SETB1111111111111111111111111111111111111111A1111111111111111111111111111111111111111911111111111
S1C6200/6200A CORE CPU MANUAL EPSON 253 INSTRUCTION SETB11111111111111111111111111111111A111111111111111111111111111111119111111111111111111111111111
26 EPSON S1C6200/6200A CORE CPU MANUAL3 INSTRUCTION SET3.2 OperandsThis section describes the operands used in the instructions.p 5-bit immediate dat
S1C6200/6200A CORE CPU MANUAL EPSON 273 INSTRUCTION SET3.4 Instruction TypesInstructions are divided into six types according to the size of the oper
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
S1C6200/6200A CORE CPU MANUAL EPSON iCONTENTSCONTENTS1DESCRIPTION ____________________________________________________ 11.1 System Features ...
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
S1C6200/6200A CORE CPU MANUAL EPSON 11 DESCRIPTION1DESCRIPTIONThe S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microco
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
2 EPSON S1C6200/6200A CORE CPU MANUAL1 DESCRIPTIONFig. 1.1 Block diagramI DZCALUS1C6200 CORE CPU4-bit address bus8-bit address bus13-bit address bus
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:Source Format:Operation:OP-Code:Type:Clock Cycles:Flag:Description:Example:
S1C6200/6200A CORE CPU MANUAL EPSON 32 MEMORY AND OPERATIONS2MEMORY AND OPERATIONSA single-chip microcomputer using the S1C6200/6200A Core CPU has fo
84 EPSON S1C6200/6200A CORE CPU MANUALAPPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPUAPPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPUS1C6200A is an i
S1C6200/6200A CORE CPU MANUAL EPSON 85APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPUb) At HALT modec) During "PSET" instruction executionF
86 EPSON S1C6200/6200A CORE CPU MANUALAPPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU<Reference 1> Writing on the interrupt mask register durin
S1C6200/6200A CORE CPU MANUAL EPSON 87APPENDIX B. INSTRUCTION INDEXAPPENDIX B. INSTRUCTION INDEXACPX MX,r Add with carry r-register to M(X), incremen
88 EPSON S1C6200/6200A CORE CPU MANUALAPPENDIX B. INSTRUCTION INDEXLBPX MX,e Load immediate data e to memory, and increment X by 2 ...
S1C6200/6200A CORE CPU MANUAL EPSON 89APPENDIX B. INSTRUCTION INDEXPUSH r Push r-register onto stack ...
AMERICAEPSON ELECTRONICS AMERICA, INC.- HEADQUARTERS -150 River Oaks ParkwaySan Jose, CA 95134, U.S.A.Phone: +1-408-922-0200 Fax: +1-408-922-0238- S
Core CPU ManualS1C6200/6200AEPSON Electronic Devices WebsiteELECTRONIC DEVICES MARKETING DIVISIONFirst issue February, 1989Printed February, 2001 in J
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